1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof. More particularly, the present invention relates to an arrangement of capacitors formed above transfer gate in memory cell portion.
2. Description of the Background Art
Conventional semiconductor device is described with reference to FIGS. 11 to 14. FIG. 11 is a plan view of memory cell portion of the semiconductor device. In order to explain relative position of each portion, the drawing assumes that all interlayer insulating layers actually filling spaces between each portion are transparent. FIG. 12 shows a cross-sectional view cut along a centerline of bit line 6 shown in FIG. 11, i.e., a cross-section with respect to the line XIIxe2x80x94XII viewed in the direction of arrows. FIG. 13 shows a cross-sectional view cut along a centerline of capacitor 14 shown in FIG. 11, i.e., a cross-section with respect to the line XIIIxe2x80x94XIII viewed in the direction of arrows. A plurality of transfer gates 2 are formed linearly and in parallel with each other such that they protrude above the main surface of semiconductor substrate 1 such as silicon wafer. Within a space between these transfer gates 2, a lower layer contact 4a each made of conductive material is formed such that it is connected to each bit line 6 with a regular spacing, to have a shape of approximate ellipse whose major axis is parallel to longitudinal direction of said transfer gate 2. As shown in FIG. 12, lower layer contact 4a is electrically connected to main surface of semiconductor substrate 1. Upper side of transfer gate 2 is covered with an interlayer insulating layer 3.
As shown in FIG. 12, a bit line contact 7 is electrically connected from above lower layer contact 4a. Bit line contact 7 is for electrically connecting bit line 6 of conductive material extending horizontally over transfer gate 2 with lower layer contact 4a. The section over lower layer contact 4a and under bit line 6 is filled with interlayer insulating layer 5. The section over bit line 6 is filled with interlayer insulating layer 8.
As shown in FIG. 13, a plurality of capacitors 14 arranged over transfer gate 2 are so-called concave type capacitors. These are cup-type condensers each having a bottom surface on its lower end, and its upper ends open. When cut along a horizontal plane, their cross-sectional shape look like two semicircles opposing to each other with a short distance, joined by parallel sides as shown in FIG. 11. Along this cup-type form, two conductive material parts called storage node 11 and cell plate cylindrical portion 12 contact with an insulating layer (not shown) interposed, forming a condenser. Storage node 11 covers outer side of the cup-type form, and is electrically connected to lower layer contact 4b formed inside the space between transfer gates 2 by storage node contact 9. Therefore, there are two kinds of lower layer contact: lower layer contact 4a connecting bit line contact 7, and lower layer contact 4b connecting storage node contact 9. The section over storage node contact 9 where capacitor 14 does not exist is filled with interlayer insulating layer 10. Upper surface of interlayer insulating layer 10 is covered with cell plate upper surface portion 13 which is of a conductive material. Cell plate upper surface portion 13 is connected to cell plate cylindrical portion 12. Cell plate upper surface portion 13 and storage node 11 are insulated by intermediate insulating layer (not shown) interposed therebetween.
This capacitor 14 is a condenser which is desired to have larger capacity. If it has constant thickness (distance from top to bottom in FIG. 13), it is desirable to enlarge cross-sectional shape of capacitor 14 to obtain larger capacity. In addition, in the case of concave type capacitor, when the aspect ratio as a value of its depth divided by width becomes too large, problem such as defective embedding of electrode material within capacitor 14 or degradation of etching shape may occur. From this aspect, it is also desired to enlarge the cross-sectional shape.
As shown in FIG. 11, conventional capacitors 14 are each arranged directly above each storage node contact 9 with its center corresponding to the center of storage node contact 9; as the result, capacitors are aligned in square. FIG. 14 extracts and shows only this arrangement of capacitors 14.
Enlargement of cross-sectional shape of capacitor 14 will be described referring to dimensions a, b, c, and d shown in FIG. 14. When enlarging the size of individual capacitor 14 with the arrangement of capacitors 14 themselves kept as it is, it is theoretically possible to enlarge two parameters a and b respectively. Processing of capacitor 14 will be difficult, however, if only a becomes longer and the ratio a/b becomes extremely large. Therefore, both a and b must be enlarged together to enlarge the shape of capacitor 14.
On the other hand, thickness of interlayer insulating layer 10 which separates neighboring capacitors 14 must be larger than a prescribed value to avoid neighboring capacitors 14 effecting each other as condensers. When a and b are enlarged together, d rather than c will become the first problem for the thickness of interlayer insulating layer 10. Since the distance d must have at least a prescribed value, enlargement of a is limited so that there is a dead space 15 in the area surrounded by four capacitors 14 as shown in FIG. 11.
Therefore, an object of the present invention is to provide a semiconductor device which can minimize dead space in the arrangement of capacitors and maximize shape of individual capacitor, and a method of manufacturing the semiconductor device.
To accomplish the above-mentioned object, the semiconductor device according to the present invention includes a semiconductor substrate having a main surface, a plurality of transfer gates formed on the main surface and extending linearly in parallel with each other, lower layer contacts each formed of a conductive material, so as to electrically connect to the main surface in a plurality of spaces respectively formed between the plurality of transfer gates, a plurality of storage node contacts each formed of rod-shaped conductive material extending upwards, and arranged with electrical connection to upper surface of selected ones of the lower layer contacts, and a capacitor formed to have an approximately elliptical cross-sectional shape whose major axis is perpendicular to longitudinal direction of the transfer gate and extending upwards from upper surface of each storage node contact, wherein when the arrangement of the capacitors is seen vertically from above the main surface, rows of capacitors are formed such that, along direction of the major axis, the plurality of capacitors are aligned with regular intervals with a pitch therebetween corresponding approximately two times the sum of width of one transfer gate and width of one space between transfer gates, and when arbitrary one of the capacitor rows is taken as a first capacitor row, a second capacitor row which is another capacitor row is arranged adjacent to and in parallel therewith, and capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by the length corresponding approximately to the sum of width of one transfer gate and width of one space between the transfer gates. In this structure, arrangement of capacitors would not be a simple square-shape, and since neighboring capacitor rows are made out of phase with each other by a certain amount, ellipse of individual capacitor can further be enlarged without interfering with ellipse of each capacitor belonging to the neighboring capacitor row.
In the invention above, preferably, when the storage node contacts aligned with electrical connection to upper surface of each of the lower layer contacts aligned in one arbitrary space between the transfer gates is looked from above, the capacitors overlap with centers of the approximate ellipses shifted alternately in opposite sides. By this structure, even if arrangement of storage node contacts has the conventional square shape, new capacitor arrangement based on the present invention described above can be provided thereabove, thereby ensuring connection to storage node contact of each capacitor effectively and reliably.
In the invention above, preferably, when arbitrary one of the capacitors is taken as a specific capacitor, among other surrounding capacitors, the capacitor diagonally adjacent to it in the direction of the major axis is the closest to above-mentioned specific capacitor. By this structure, wasteful space of the capacitor arrangement can be made as small as possible.
In the invention above, preferably the semiconductor device includes a plurality of bit lines arranged in parallel with each other and extending perpendicular to the transfer gate in a plane positioned above upper end of the transfer gate and below lower end of the capacitor, and electrically connected to selected lower layer contacts via bit line contacts extending downward from the bit lines. By this structure, since the bit lines are arranged below the capacitors, the difficulty in arranging bit line contacts due to the arrangement of capacitors can be avoided.
In the invention above, preferably the capacitor includes a storage node and a cell plate, wherein the storage node is a conductor electrically connected to the storage node contact, having a cross-sectional shape of approximate ellipse and formed as container type having a bottom surface on the lower end and open upper end, while the cell plate is a conductor covering inner surface of the storage node with insulating layer posed therebetween. By this structure, cross-sectional area of each capacitor can be enlarged to make a concave type capacitor with reduced embedding defect or etching shape defect.
In the invention above, preferably the capacitor includes a storage node and a cell plate, wherein the storage node is a conductor electrically connected to the storage node contact and is formed in solid, approximate elliptic cylinder form, and the cell plate is a conductor covering outer surface of the storage node with insulating layer posed therebetween. By this structure, since each capacitor has an ellipse shape which can be enlarged sufficiently in the direction of its minor axis, the space between capacitors in the direction of major axis can have sufficient margin and the capacitor can be made as a convex type capacitor with reduced probability of short circuit resulting, for example, from intervening microscopic foreign matters between capacitors.
To accomplish the above-mentioned object, the method of the present invention is a method of manufacturing a semiconductor device which includes a semiconductor substrate having a main surface, a plurality of transfer gates formed on the main surface and extending linearly in parallel with each other, lower layer contacts each formed of a conductive material, so as to electrically connect to the main surface in a plurality of spaces respectively formed between the plurality of transfer gates, a plurality of storage node contacts each formed of rod-shaped conductive material extending upwards, and arranged with electrical connection to upper surface of selected ones of the lower layer contacts, and a capacitor formed to have an approximately elliptical cross-sectional shape whose major axis is perpendicular to longitudinal direction of the transfer gate and extending upwards from upper surface of each storage node contact, wherein, in order to form the capacitor, the method comprises a platemaking step of performing platemaking for resist applied on upper surface to form resist pattern using platemaking mask pattern, and an etching step of etching with the resist pattern obtained from the platemaking step, wherein arrangement of the platemaking mask pattern is such that, along direction of the major axis, the plurality of capacitors are aligned with regular intervals with a space therebetween being approximately the width of one transfer gate, forming capacitor rows, and when arbitrary one of the capacitor rows is taken as first capacitor row, a second capacitor row which is another capacitor row is arranged adjacent to and in parallel therewith, and capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by the length corresponding approximately to the sum of width of one transfer gate and width of one space between the transfer gates. By this method, the semiconductor device can be obtained of which capacitor has not a simple square-shape but an arrangement in which neighboring capacitor rows are made out of phase with each other by a prescribed amount. Thus, semiconductor device having capacitors with enlarged cross-sectional shape can be obtained.
In the invention above, as above-mentioned platemaking mask pattern, it is preferable to use the platemaking mask pattern having cross pattern at portions where approximate ellipse pattern should be formed. By this method, platemaking mask pattern for forming approximate ellipse shape capacitor can be provided only with straight lines, even if it is impossible to make platemaking mask pattern of curved figure.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.